This invention relates to a method of manufacturing a semiconductor device, in which a wiring metal layer of a desired size and pattern is formed on the surfaces of semiconductor regions formed in a semiconductor substrate.
In the semiconductor device, in which a wiring metal layer of a desired size and pattern is formed on the surfaces of semiconductor regions formed in a semiconductor substrate, the wiring metal layer is usually formed by covering the semiconductor substrate with a silicon oxide film after forming, if necessary, a semiconductor region or semiconductor regions in the substrate, forming contact holes in predetermined portions of the silicon oxide film by using a mask, depositing a wiring metal on the entire silicon oxide film inclusive of the contact holes and selectively etching the wiring metal by using a mask to thereby form a desired wiring pattern.
This prior-art method, however, includes several mask alignment steps and also etching steps for obtaining the desired wiring metal pattern. Since the mask alignment step inevitably involves some deviation from the proper alignment between the mask and semiconductor substrate, the pattern formed on the semiconductor device formed on the semiconductor substrate must have extra dimensions to take up the possible deviation from the proper mask alignment. This means that the several mask alignment steps are not only tedious, but are also undesiredfrom the standpoint of the improvement of the integration density of the device. In addition, at the time of the etching for the patterning of the wiring metal using a photoresist, the width of the wiring metal layer is made narrower than that of the photoresist due to what is called side etching, so that in order to obtain a wiring pattern having a desired width it is necessary to provide a photoresist pattern having an extra width corresponding to the amount of side etching, which is undesired from the standpoint of the improvement of the density of integration.
As an example of the prior-art method of manufacturing a semiconductor device, such as the one shown in FIG. 1, reference is made to a method in which the wiring is formed by a lift-off method. Such a method is disclosed in the "Semiconductor Transistor Research Institute", 1978, SSD78-65, page 33. In this method, a silicon oxide film 8 formed on a principal surface of a semiconductor substrate 7, which comprises a p-type silicon substrate 1, an n.sup.+ -type burried layer 2, an n-type epitaxial layer 3, isolation layers 4, a p.sup.+ -type base region 5 and an n.sup.+ -type collector region 6, is formed with base and collector contact holes 9 and 10 and an emitter diffusion hole 11, and an n.sup.+ -type emitter region 12 is formed by ion implanting arsenic with the base contact hole 9 covered with a photoresist. Subsequently, a polyimide resin film 13 and a metal film 14 of such metal as chromium are formed on the principal surface of the semiconductor substrate 7, and the metal film 14 is then subjected to dry etching using a photoresist mask to form openings corresponding to the contact holes 9 and 10 and diffusion hole 11. Thereafter, the polyimide film 13 is etched with a hydrazine hydrate solution and with the metal film 14 as a mask to form holes greater in diameter than the openings in the metal film 14, and then a wiring metal 15, for instance aluminum, is deposited on the entire surface (see FIG. 1). Afterwards, the polyimide resin film 13 is removed to lift off the aluminum portions 15 on the metal film 14.
In the above method, after the formation of the base and collector contact holes 9 and 10 and emitter diffusion hole 11, the polyimide resin film 13 and chromium or like metal film 14 are selectively etched in a separate step for the purpose of lifting off the wiring metal. This means that it is necessary to provide sufficient mask alignment redundancy for the etching of the polyimide resin film 13 and metal film 14. In addition, in the formation of the openings in the metal film 14 it is likely that they are not formed in self alignment to the base and collector contact holes 9 and 10 and emitter diffusion hole 11 as shown in FIG. 1. In such a case, it is likely that the contact between the emitter region 12 and associated wiring is adversely affected to reduce the yield.